Technical Field
The present invention relates to semiconductor devices and processing, and more particularly to dual liner silicides for complementary metal oxide semiconductor (CMOS) devices.
Description of the Related Art
Complementary metal oxide semiconductor (CMOS) processing is often different for N-type field effect transistors (NFETs) versus P-type field effect transistors (PFETs). This is pertinent for silicided liners formed for landing contacts in both the NFETs and the PFETs. The dual silicide refers to the formation of silicided contact liners for both NFETs and PFETs in a single process flow. Conventional ways to form dual liner silicides include the following techniques.
In one method, a contact trench is formed and a first liner material is deposited for the NFET. Then, a mask is formed over the first liner material, and the first liner material is removed from the PFET. A second liner material is formed for the PFET. Then, metallization is formed from both the NFET and PFET. In this method, a metal liner is exposed to ash and the first liner material can undergo metal mixing with the PFET source and drain (S/D) regions.
In another method, a contact trench is formed followed by a first liner material being deposited, followed by a metal fill (e.g., Tungsten, or other sacrificial material). The metal fill and the first liner material are removed from the PFET. A second liner material is deposited and metallization is formed. In this method, as before, the first liner material can metal mix with the PFET S/D regions.
In another method, contacts are formed for the NFET and the PFET. The NFET contacts are etched and a first liner and metal fill are performed. Then, the PFET contacts are etched and a second liner and metal fill are performed. At least 2 additional lithography steps are needed in this method.